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TDA7339
3 BAND DIGITAL CONTROLLED AUDIO PROCESSOR
PRODUCT PREVIEW
THREE STEREO INPUT ONE RECORD OUTPUT ONE STEREO OUTPUT TWO INDEPENDENT VOLUME CONTROL IN 1.0dB STEPS TREBLE, MIDDLE AND BASS CONTROL IN 1.0dB STEPS ALL FUNCTIONS PROGRAMMABLE VIA SERIAL I2 CBUS DESCRIPTION The TDA7339 is a volume and tone (bass , middle and treble) processor for quality audio application in car radio and Hi-Fi system. Control is accomplished by serial I2C bus microprocessor interface. The AC signal setting is obtained by resistor networks and switches combined with operational amplifiers. BLOCK DIAGRAM
DIP28
ORDERING NUMBER: TDA7339
Thanks to the used BIPOLAR/MOS Technology, Low Distortion, Low Noise and Low DC stepping are obtained.
R1 2.7K C7 5.6nF 3x 2.2F C1 C2 C3 REC OUT(L) TREBLE(L) 2 4 5 MUTE 8 1st VOL TREBLE MIDDLE 3 C9 18nF M IN(L) 6 C10 22nF M OUT(L) 7 9 C13 100nF B IN(L)
R3 2.7K C14 100nF B OUT(L) 10 2nd VOL BASS SOFTMUTE
IN1(L) IN2(L) IN3(L)
12
OUT L
14 13 SERIAL BUS DECODE & LATCHES 18 15 1st VOL TREBLE MIDDLE BASS 2nd VOL SOFTMUTE 17 11
SCL SDA ADDR DIG.GND CMUTE CSM 22nF OUT R BUS
MULTIPLEXER
IN1(R) IN2(R) IN3(R)
C4 C5 C6 3x 2.2F
27 25 24 MUTE
1 VS SUPPLY 16 ANAL.GND CREF 28 21 26 M IN(R) C11 18nF 23 M OUT(R) C12 22nF R2 2.7K 22 20 B IN(R) C15 100nF R4 5.6K 19 B OUT(R) C16 100nF
D94AU067C
REC OUT(R) TREBLE(R) CREF 10F C8 5.6nF
July 1999
This is preliminary information on a new product now in development. Details are subject to change without notice.
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TDA7339
ABSOLUTE MAXIMUM RATINGS
Symbol VS Tamb Tstg Operating Supply Voltage Operating Ambient Temperature Storage Temperature Range Parameter Value 10.5 -40 to 85 -55 to 150 Unit V C C
PIN CONNECTION
VS IN1L TREBLE L IN2L IN3L M IN L M OUT L REC OUT L B IN L B OUT L CMUTE OUT L SDA SCL
1 2 3 4 5 6 7 8 9 10 11 12 13 14
D95AU217A
28 27 26 25 24 23 22 21 20 19 18 17 16 15
CREF IN1R TREBLE R IN2R IN3R M IN R M OUT R REC OUT R B IN R B OUT R ADDR OUT R AGND DIG GND
THERMAL DATA
Symbol Rth j-amb Parameter Thermal Resistance Junction-pins Value 65 Unit C/W
QUICK REFERENCE DATA
Symbol VS VCL THD S/N SC Supply Voltage Max. input signal handling Total Harmonic Distortion V = 1Vrms f = 1KHz Signal to Noise Ratio Channel Separation f = 1KHz 1st and 2nd Volume Control 1dB step Bass, Middle and Treble Control 1dB step Mute Attenuation -47 -14 100 Parameter Min. 6 2 0.01 106 100 0 +14 0.08 Typ. 9 Max. 10 Unit V Vrms % dB dB dB dB dB
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TDA7339
ELECTRICAL CHARACTERISTICS (VS = 9V; RL = 10K; f = 1KHz; all control = flat (G = 0); Tamb = 25C Refer to the test circuit, unless otherwise specified.)
Symbol Parameter Test Condition Min. Typ. Max. Unit
INPUTS
R in C RANGE AVMAX Astep EA Et Amute VDC Input Resistance 35 50 65 K
1st VOLUME CONTROL
Control Range Maximum Attenuation Step Resolution Attenuation Set Error Tracking Error Mute Attenuation DC Steps 45 45 0.5 -1.0 -1.5 47 47 1.0 49 49 1.5 1.0 1.5 1 2 100 0 0.5 3 5 dB dB dB dB dB dB dB dB mV mV
G = 0 to -24dB G = -24 to -47dB G = 0 to -24dB G = 24 to -47dB Adiacent Attenuation Steps From 0dB to AVMAX
80
2nd VOLUME CONTROL
C RANGE AVMAX Astep EA Et AMUTE VDC Control Range Maximum Attenuation Step Resolution Attenuation Set Error Tracking Error Mute Attenuation DC Steps G = 0 to -24dB G = -24 to -47dB G = 0 to -24dB G = 24 to -47dB 80 Adiacent Attenuation Steps From 0dB to AVMAX 100 0 0.5 45 45 0.5 -1.0 -1.5 47 47 1.0 49 49 1.5 1.0 1.5 1 2 3 5 dB dB dB dB dB dB dB dB mV mV
BASS
Rb C RANGE Astep Internal Feedback Resistance Control Range Step Resolution 32 11.5 0.5 44 14 1 56 16 1.5 K dB dB
MIDDLE
Rb C RANGE Astep Internal Feedback Resistance Control Range Step Resolution 18 11.5 0.5 13 0.5 25 14 1 14 1 32 16 1.5 15 1.5 K dB dB
TREBLE
C RANGE Astep Control Range Step Resolution dB dB
SUPPLY
VS IS SVR Supply Voltage (note1) Supply Current Ripple Rejection 6 4 60 9 7 90 10.5 10 V mA dB
SOFT MUTE
AMUTE tD Mute Attenuation Delay Time C SM = 22F; 0 to 20dB; I = IMAX C SM = 22F; 0 to 20dB; I = IMIN 45 0.8 15 60 1.5 25 2 45 dB ms ms
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TDA7339
ELECTRICAL CHARACTERISTICS (continued)
Symbol Parameter Test Condition Min. Typ. Max. Unit
AUDIO OUTPUT
Vclip R Ol RO VDC Clipping Level Output Load Resistance Output Impedance DC Voltage Level d = 0.3% 2 2 100 180 3.8 300 2.6 Vrms K V V dB dB dB dB 0.08 %
GENERAL
eNO Et S/N SC d Output Noise Total Tracking Error Signal to Noise Ratio Channel Separation Distortion AV = 0; V in = 1Vrms All Gains 0dB (B = 20 to 20kHz flat) AV = 0 to -24dB AV = -24 to -47dB All Gains = 0dB; VO = 1Vrms 80 5 0 0 106 100 0.01 15 1 2
BUS INPUTS
V il Vih Iin VO Input Low Voltage Input High Voltage Input Current Output Voltage SDA Acknowledge Vin = 0.4V IO = 1.6mA 3 -5 0.4 5 0.8 1 V V A V
NOTE 1: the device is functionally good at Vs = 5V. A step down, on V S, to 4V does't reset the device.
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TDA7339
I2C BUS INTERFACE Data transmission from microprocessor to the TDA7319 and viceversa takes place thru the 2 wires I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be externally connected). Data Validity As shown in fig. 3, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. Start and Stop Conditions As shown in fig.4 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. Byte Format Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first. Data Validity on the I 2CBUS Acknowledge The master (P) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 5). The peripheral (audioprocessor) that acknowledges has to pull-down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse. The audioprocessor which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer. Transmission without Acknowledge Avoiding to detect the acknowledge of the audioprocessor, the P can use a simplier transmission: simply it generates the 9th clock pulse without checking the slave acknowledging, and then sends the new data. This approach of course is less protected from misworking and decreases the noise immunity.
Timing Diagram of I2CBUS
Acknowledge on the I2CBUS
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TDA7339
SOFTWARE SPECIFICATION Interface Protocol The interface protocol comprises: A start condition (s) A chip address byte, containing the TDA7339 address (the 8th bit of the byte must be 0). The TDA7339 must always acknowledge at the end of each transmitted byte. A sequence of data (N-bytes + acknowledge) A stop condition (P)
TDA7339 ADDRESS
MSB S 1 0
first byte 0 0 0 1 A
LSB 0 ACK
MSB DATA
LSB
ACK
MSB DATA
LSB
ACK P
Data Transferred (N-bytes + Acknowledge) ACK = Acknowledge S = Start P = Stop MAX CLOCK SPEED 100kbits/s
SOFTWARE SPECIFICATION Chip address
1 MSB 0 0 0 0 1 A 0 LSB
A = Logic level ON pin ADDR
FUNCTION CODES
MSB 1st VOLUME 2nd VOLUME TREBLE MIDDLE BASS MUTMUX 0 0 1 1 1 1 F6 F6 F6 0 0 1 1 F5 F5 F5 0 1 0 1 F4 F4 F4 F4 F4 F4 F4 F3 F3 F3 F3 F3 F3 F3 F2 F2 F2 F2 F2 F2 F2 F1 F1 F1 F1 F1 F1 F1 LSB 0 1 F0 F0 F0 F0
POWER ON RESET: 1st volume = 2nd volume = Mute Treble = Middle = Bass = -14dB Mutmux = Active Input IN 1
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TDA7339
1st VOLUME CODES
MSB 0 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 F6 F5 F4 F3 F2 F1 LSB 0 FUNCTION step 1dB 0dB -1dB -2dB -3dB -4dB -5dB -6dB -7dB step 8dB 0dB -8dB -16dB -24dB -32dB -40dB MUTE
2nd VOLUME CODES
MSB 0 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 F6 F5 F4 F3 F2 F1 LSB 1 FUNCTION step 1dB 0dB -1dB -2dB -3dB -4dB -5dB -6dB -7dB step 8dB 0dB -8dB -16dB -24dB -32dB -40dB MUTE
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TDA7339
TREBLE CODES
MSB 1 F6 0 F5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 F4 F3 F2 F1 LSB FUNCTION TREBLE BOOST 0dB 1dB 2dB 3dB 4dB 5dB 6dB 7dB 8dB 9dB 10dB 11dB 12dB 13dB 14dB 14dB TREBLE CUT 0dB -1dB -2dB -3dB -4dB -5dB -6dB -7dB -8dB -9dB -10dB -11dB -12dB -13dB -14dB -14dB
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TDA7339
MIDDLE CODES
MSB 1 F6 0 F5 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 F4 F3 F2 F1 LSB FUNCTION MIDDLE BOOST 0dB 1dB 2dB 3dB 4dB 5dB 6dB 7dB 8dB 9dB 10dB 11dB 12dB 13dB 14dB 14dB MIDDLE CUT 0dB -1dB -2dB -3dB -4dB -5dB -6dB -7dB -8dB -9dB -10dB -11dB -12dB -13dB -14dB -14dB
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TDA7339
BASS CODES
MSB 1 F6 1 F5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 F4 F3 F2 F1 LSB FUNCTION BASS BOOST 0dB 1dB 2dB 3dB 4dB 5dB 6dB 7dB 8dB 9dB 10dB 11dB 12dB 13dB 14dB 14dB BASS CUT 0dB -1dB -2dB -3dB -4dB -5dB -6dB -7dB -8dB -9dB -10dB -11dB -12dB -13dB -14dB -14dB
MUTMUX CODES
MSB 1 F6 1 F5 1 X X X X X X X X X X 0 0 1 1 X X X 0 1 0 1 0 0 1 0 1 X F4 F3 F2 F1 LSB FUNCTION INPUTS SLOW SOFT MUTE SLOPE (I=IMIN) FAST SOFT MUTE SLOPE (I=IMAN) SOFT MUTE OFF NOT ALLOWED IN3 IN2 IN1
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TDA7339
DIM. MIN. a1 b b1 b2 D E e e3 F I L 4.445 3.3 15.2 2.54 33.02 14.1 0.175 0.23 1.27 37.34 16.68 0.598 0.100 1.300 0.555 mm TYP. 0.63 0.45 0.31 0.009 0.050 1.470 0.657 MAX. MIN. inch TYP. 0.025 0.018 0.012 MAX.
OUTLINE AND MECHANICAL DATA
DIP28
0.130
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TDA7339
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 1999 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com
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